The present invention relates to a semiconductor device.
A microcomputer is provided in various apparatuses and performs control of each component included in the apparatus. The microcomputer includes, for example, a central processing unit (CPU) at its center, a ROM (read-only memory) for holding a program, a RAM (random access memory) for holding data, and an input/output functional block such as an input/output circuit for performing input/output of data and signals. In a semiconductor device called a single chip microcomputer, the CPU and these functional blocks are formed over the same semiconductor substrate.
When controlling various apparatuses, the microcomputer is required to perform predetermined processing on the input/output functional block responding to, for example, an event such as an interrupt from the input/output functional block. For example, although the CPU can implement arbitrary processing by a combination of commands, when performing interrupt processing, the CPU needs to switch a processing flow by performing exception processing, a stack saving/restoring operation, a restoration command, and the like. In this case, the load of the CPU increases.
On the other hand, Japanese Unexamined Patent Application Publication No. 2008-250987 discloses a data processor and a control system that provide an event response control technique that realizes high-speed data processing and CPU load reduction. As the data processor, separately from an interrupt controller, an event link controller is employed that outputs a start control signal of an operation corresponding to a circuit module responding to a generated event signal.
The circuit module can generate an event signal, and the event link controller generates the start control signal according to a correspondence between the event signal defined by event control information and the start control signal. A linkage between the event signal and the start control signal is defined by event storage information, so that operations of a plurality of circuit modules defined by the linkages are sequentially controlled. The saving/restoring operation by the CPU, which is required in the interrupt processing, is not required, and priority level control on competing interrupt requests is not required.